Announcing a new book titled:

Delay Insensitive Circuits

Structures, Semantics, and Strategies

a self-contained, full length tutorial treatment of delay insensitive circuits suitable for independent study at the graduate or professional levels


The design of concurrent distributed hardware systems is a major challenge for engineers today and is bound to escalate in the future, but engineering education continues to emphasize traditional tools of logic design that are just not up to the job. For engineers tackling realistic projects, improvised attempts at synchronization across multiple clock domains have long been a fact of life. Prone to hazards and metastability, these ad hoc interfaces could well be the least trustworthy aspects of a system, and typically also the least able to benefit from any readily familiar textbook techniques of analysis or verification.

Progress in the long run depends on a change of tactics. Instead of the customary but inevitably losing battle to describe complex systems in terms of their stepwise time evolution, taking their causal relationships and handshaking protocols as a starting point cuts to the chase by putting the emphasis where it belongs. This way of thinking may call for setting aside a hard earned legacy of practice and experience, but it leads ultimately to a more robust and scalable methodology.

Delay insensitive circuits rely on local coordination and control from the ground up. The most remarkable consequence of adhering to this course is that circuits can get useful things done without any clock distribution network whatsoever. Because a handshake acknowledgment concludes each interaction among primitive components and higher level subsystems alike, a clock pulse to mark them would be superfluous. This effect can bring a welcome relief to projects whose timing infrastructure would otherwise tend to create more problems than it solves.

The theory of delay insensitive circuits is not new but has not yet attracted much attention outside of its research community. At best ignored and at worst discouraged in standard curricula, this topic until now has been accessible only by navigating a sea of conference papers and journal articles, some of them paywalled. Popular misconceptions and differing conventions about terminology and notation have posed further barriers to entry. To address this need, this book presents a unified account of delay insensitive circuits from first principles to cutting edge concepts, subject only to an undergraduate-level understanding of discrete math. In an approachable tutorial format with numerous illustrations, exercises, and over three hundred references, it guides an engineering professional or advanced student towards proficiency in this extensive field.

Content overview

Ramping up

Delay insensitive circuits entail ways of thinking that may be unfamiliar to many readers, so a leisurely non-technical introduction across several chapters lays the foundation for more technical material to follow.

Core concepts

What are delay insensitive circuits good for? How well do they scale? How can we be sure that an optimization preserves functional correctness? How do we establish the compatibility of one circuit with another, or with a specification?


Decentralized timing gives rise to a rich assortment of components rarely seen elsewhere. From a small core of custom primitives come building blocks such as arbiters, decision waits, transcoders, completion detectors, and micropipelines in many variations.

Communication protocols

Transferring data in a self-delimiting way without wasting channel capacity, knowing when to use dual rail and optimal balanced codes, designing circuits to convert between word formats on the fly and maybe in parallel, what could go wrong?

Automated synthesis

Can an algorithm take a design from a short, abstract, unrestricted behavioral description to a verifiably correct netlist of primitive components, end to end without manual intervention? Several feasible algorithms for doing  just that are fully developed in the final chapters.


Optional advanced topics include critical path and complexity analysis for arbiters and decision waits,  modeling of fairness and contention in arbiters, and a semantics for delay insensitive processes based on the mathematical theory of complete partial orders and fixed points.